1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for performing a tool scheduling process, which includes matching a particular process with an appropriate tool.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure. Typically, forming trenches across the semiconductor wafer and filling such trenches with an insulating material, such as silicon dioxide, form STI structures across the semiconductor wafers.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on approximately one to four die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed across the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a flow chart illustration of a prior art process flow is illustrated. A manufacturing system processes a lot/batch of semiconductor wafers 105 (block 210). The manufacturing system then generally acquires metrology data relating to the processed semiconductor wafers 105 (block 220). The manufacturing system may also acquire manufacturing-environment data, such as pressure data, temperature data, humidity data, gas flow rate data, and the like. Generally, the manufacturing system then analyzes the metrology data and/or the manufacturing-environment data to determine whether there are appreciable errors across the processed semiconductor wafers 105 (block 230).
The manufacturing system may then perform a feedback correction on processes performed on the semiconductor wafers 105 based upon the analysis of the metrology/manufacturing-environment data (block 240). Utilizing current manufacturing methods, efficient matching of a particular process to the best available processing tool may not occur without tedious manual intervention. Furthermore, isolation and/or tagging of particular processing tools that may be lagging behind other processing tools, in terms of efficiency and accuracy of processing, may not timely occur.
Among the problems associated with implementing the current processes include the fact that some processing tools may perform certain processes on particular layers of a semiconductor wafer 105 in an inefficient or inaccurate manner. For example, some processing tools may process the fourth layer of semiconductor wafers 105 in a lot in an inefficient or inaccurate manner (e.g., an etch process that may not be timed and executed well by a particular processing tool), but may be more efficient in processing layers 1 through 3. This could lead to inefficiency in manufacturing of semiconductor devices. Furthermore, this could lead to an increased number of errors and faults on the processed semiconductor wafers 105. The state of the art processes include routing semiconductor wafers in a sequential manner without much regard to the actual efficiency of each processing tool on particular layers of processed on semiconductor wafers 105. This could lead to inefficiency in semiconductor device manufacturing.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.